1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a flash memory device and a method for manufacturing the same.
2. Background of the Related Art
General memory devices are divided into a read only memory (hereinafter referred to as ROM) and a random access memory hereinafter referred to as RAM). ROMs are divided into a mask ROM and a programmable ROM (PROM). In a mask ROM, a program data is inputted into a mask in advance to program the ROM. In a PROM, a chip is fabricated and mounted and then a ROM is programmed.
A PROM is again divided into an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM). In an EPROM, inputted data can be erasable by means of ultraviolet ray. In an EEPROM, inputted data can be electrically erasable.
In a flash memory device of a three layered gate type, an erase gate is formed in an EEPROM cell so that inputted data may be electrically erasable. Also, in a flash memory device of a two layered gate type, an electric field is emitted toward a source.
FIG. 1a is a plan view of a related art flash memory device, FIG. 1b is a cross-sectional view showing the structure of the related art flash memory device, taken along line I-I' of FIG. 1a, FIG. 1c is a cross-sectional view showing the structure of the related art flash memory device, taken along line II-II' of FIG. 1a, and FIG. 1d is an equivalent circuit diagram of FIG. 1a.
A related art flash memory device, as shown in FIGS. 1a to 1c, includes a plurality of buried heavily doped impurity regions 2 spaced away from one another by a predetermined distance by implanting heavily n.sup.+ type impurity ions into a p-type semiconductor substrate 1. A plurality of isolation oxide layers 3 is formed at a right angle to the plurality of the buried heavily doped impurity regions 2. First sidewall spacers 3a are formed on both sides of each of the isolation oxide layers 3, and a gate oxide layer 4 is formed on the entire surface of the semiconductor substrate 1 exclusive of the isolation oxide layers 3 and the first sidewall spacers 3a.
Each of the floating gates 5b overlaps each of the buried heavily doped impurity regions 2 by a predetermined area, and a first interlevel insulating film 6 is formed on the entire surface of the semiconductor substrate 1 inclusive of the floating gates 5b. A control gate line 7a and a cap oxide layer 8 are successively formed on the first interlevel insulating film 6 and have a narrower width than the floating gate 5b. Second sidewall spacers 9 are formed on both sides of the control gate line 7a and the cap oxide layer 3, and an erase gate line 11a overlapping two of the control gate lines 7a. One erase gate line 11a is designed to erase electrons of the floating gate 5b formed along the erase gate line 11a.
For programming a flash memory of three layered polysilicons 5b, 7a, and 11a, a voltage of 7V is applied to the buried heavily doped impurity region 2, a voltage of 12 V is applied to the control gate 7a, and a voltage 0V is applied to the buried heavily doped impurity region 2, which is neighboring with the buried heavily doped impurity region 2 used as the drain. Channel hot electrons, which are generated by high electric field at the drain of a channel, pass over potential barrier of the gate oxide layer 4 so as to be injected to the floating gate 5b. As a result, a threshold voltage of a memory device is increased.
For erasing inputted data, a high voltage of between 12V-24V is applied to the erase gate 11a and a voltage of 0V is applied to the control gate 7a and the floating gate 5b. Accordingly, a high electric field is generated due to a sharp geometrical structure of the floating gate 5b formed on the isolation oxide layer 3 and electrons travel to the erase gate 11a, thus generating an electron tunneling known as "Fowler Nordheim tunneling" from the floating gate 5b to the erase gate 11a.
In other words, the floating gate 5b loses electrons and the threshold voltage of the memory device is decreased. The arrow shown in FIG. 1c indicates the electron movement direction during the erase operation. Accordinaly, a threshold voltage of a device is controlled and inputted data is maintained. For reading data, voltages of 5V, 1V, and 0V are applied to the control gate, the drain, and the source and the erase gate, respectively, so that changes of potential of a bitline connected to the drain, or changes of current are sensed, depending on a difference of threshold voltages according to stored data, thereby reading the stored data.
FIGS. 2a through 2i are cross-sectional views showing process steps of the related art method for manufacturing the flash memory device, taken along line I-I' of FIG. 1a. FIGS. 3a through 3i are cross-sectional views showing process steps of the related art method for manufacturing the flash memory deice, taken alone line II-II' of FIG. 1a.
First, heavily n.sup.+ impurity ions are selectively implanted into a p-type semiconductor device 1 so as to form a plurality of buried heavily doped impurity regions 2 used as source and drain, as shown in FIGS. 2a and 3a. At this time, the impurity regions 2 are spaced away from one another by a prescribed distance. An oxide layer is formed on the semiconductor substrate 1 and then is selectively patterned with a photolithography process and an photo etching process, thus forming a plurality of isolation oxide layers 3 at a right angle to the buried heavily doped impurity regions 2. Next, first sidewall spacers 3a are formed on both sides of each of the isolation oxide layers 3.
Referring to FIGS. 2b and 3b, a gate oxide layer 4 is formed on the entire surface of the semiconductor substrate 1 exclusive of the isolation oxide layers 3 and the first sidewall spacers 3a. Then, on the entire surface, a polysilicon layer 5 which will be used as a floating gate is deposited.
Referring to FIGS. 2c and 3c, a photoresist PR.sub.1 is coated on the polysilicon layer 5 and then is subjected to exposure and development to pattern and to define the placement of a floating gate line. With the photoresist pattern PR.sub.1 serving as a mask, the polysilicon layer 5 is selectively etched, and thus forming a floating gate line 5a. At this time, one edge of the floating gate line 5a overlaps the heavily doped impurity region 2 used as a drain by a predetermined area. The floating gate line 5a is offset from the heavily impurity region 2 used as a source.
Referring, to FIGS. 2d and 3d, the remaining photoresist film PR.sub.1 is removed. Subsequently, a first interlevel insulating film 6, a polysilicon layer 7 used as a control gate, a cap oxide layer 8, and a photoresist film PR.sub.2 are successively formed on the entire surface of the semiconductor substrate 1 inclusive of the floating gate line 5a, the isolation oxide layer 3, and the first sidewall spacers 3a. Thereafter, the photoresist film PR.sub.2 is subjected to exposure and development to be patterned, thus defining a placement of a control gate line.
Referring to FIGS. 2e and 3e, with the photoresist pattern PR.sub.2, serving as a mask, the cap oxide layer 8, the polysilicon layer 7, and the first interlevel insulating film 6 are selectively removed to form a control gate line 7a. At this time, the control gate line 7a is located between the isolation oxide layers 3 in the same direction as the isolation oxide layers 3. Both edges of the control gate line 7a overlap the isolation oxide layers 3 by a predetermined area.
Referring to FIGS. 2f and 3f, the remaining photoresist film PR.sub.2 is removed. An oxide layer used as sidewall spacers is deposited on the entire surface of the semiconductor substrate 1 and then is etched-back to form second sidewall spacers 9 on both sides of the cap oxide layer 8, the control gate line 7a, and the interlevel insulating layer 6.
Referring to FIGS. 2g and 3g, with the second sidewall spacers 9 serving as a mask, the floating gate line 5a is etched to form a plurality of floating gates 5b.
Referring to FIGS. 2h and 3h, on the entire surface inclusive of the cap oxide layer 8 and the second sidewall spacers 9, a second interlevel insulating film 10, a polysilicon layer 11 used as an erase gate, and a photoresist film PR.sub.3, which is then subjected to exposure and development to be patterned, thus defining a placement of an erase gate line, are successively formed. At this time, the photoresist film PR.sub.3 is patterned to overlaps two of the control gate lines 7a.
Referring to FIGS. 2i and 3i, with the photoresist pattern PR.sub.3 serving as a mask, the polysilicon layer 11 and the second interlevel insulating film 10 are selectively etched to form an erase gate line 11a, which overlaps two of the control gate lines 7a, in the same direction as the control gate lines 7a. Then, the remaining photoresist film PR.sub.3 is removed, thereby finishing the conventional flash memory device.
Such a related art flash memory device and a related art method for manufacturing the same have various disadvantages. First, since a channel between source and drain regions is used as both a control gate line and a floating gate, a high integration and high speed operations are difficult to achieve. Second, for programming, a channel hot carrier is utilized, so that a gate oxide layer is damaged and thus limitations are given to a high programming frequency.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.